The Virtuoso UltraSim simulator helped Sirific improve its time to market. Sirific designs and develops the NEXUS family of single-chip CMOS RF transceivers for 3.5G and 2.75G mobile applications. The Virtuoso UltraSim simulator enabled Sirific to cut its verification time from two weeks to eight hours, allowing development in record time while ensuring silicon accuracy critical for mixed-signal designs.
announced that Sirific Wireless Limited, a fabless RF semiconductor company, has successfully designed its single-chip CMOS RF transceiver for HSDPA/WEDGE using the Cadence Virtuoso UltraSim Full-chip Simulator for FastSPICE simulation. San Jose, CA - Cadence Design Systems, Inc.
